edge-triggered flip-flop

英 [edʒ ˈtrɪɡəd flɪp flɒp]

美 [edʒ ˈtrɪɡərd flɪp flɑːp]

网络边沿触发器; 正反器; 触发器; 边缘触发器

Three triggered ways of the flip-flop which are master-slave flip-flop, pulse flip-flop, edge-triggered flip-flop, is analyzed and compared in the paper.
分析与比较了触发器三种触发方式：电平触发、脉冲触发、边沿触发。
Ternary Edge-triggered Flip-Flop Based on Modular Algebra and its Application
基于模代数的三值维持阻塞触发器及其应用
When TTL JK edge-triggered flip-flop is in rise and fall edges of CP, its output state should arise abnormal changes.
TTLJK边沿触发器在CP脉冲边沿会出现输出状态异变现象。
Edge-triggered JK flip-flop Improved from D flip-flop
由D触发器改进的边沿JK触发器
CMOS Ternary D-Type Edge-triggered Flip-Flop Using One Latch
一种单锁存器CMOS三值D型边沿触发器设计
A Simplified Design of Edge-Triggered Flip-Flop
维持阻塞触发器的简化设计
The clock gating technique is merely applicable to single edge-triggered flip-flop. It is a special kind of clock edge control technique.
而门控时钟技术只适用于单边沿触发器，是一种特殊的时钟边沿控制技术。